Typically, a computer system includes a number of integrated circuit chips that communicate with one another to perform system applications. Chip speeds continue to increase and the amount of data communicated between chips continues to increase to meet the demands of system applications. As the volume of digital data communicated between chips increases, higher bandwidth communication links are needed to prevent data communication bottlenecks between chips.
Often, the computer system includes a controller, such as a micro-processor, and one or more memory chips, such as random access memory (RAM) chips. The RAM chips can be any suitable type of RAM, such as dynamic RAM (DRAM), double data rate synchronous DRAM (DDR-SDRAM), graphics DDR-SDRAM (GDDR-SDRAM), reduced latency DRAM (RLDRAM), pseudo static RAM (PSRAM), and low power DDR-SDRAM (LPDDR-SDRAM).
Typically, data and a strobe signal are communicated between chips, such as a controller and a RAM, via the communications link to read and write data. To write data to a chip, such as a RAM, data and a strobe signal are transmitted to the chip and the received data is sampled via the received strobe signal. To read data from the chip, data and a strobe signal are transmitted from the chip. Data and strobe signal timing are critical to reliable operation of the communications link.
Higher bandwidth communication links can be built by increasing input/output (I/O) data bit and strobe signal speeds. However, increasing I/O data bit and strobe signal speeds reduces data bit and strobe signal timing budgets, such as set up and hold times, which can lead to read and write timing problems. Sometimes, one or more delay circuits are included in critical signal paths, such as read and write data paths, to adjust signal timing. However, process variations can affect delay circuit delay times and cause race conditions, which lead to functional failures or a reduced timing budget. A reduced timing budget reduces the maximum speed of operation.
For these and other reasons there is a need for the present invention.